1. Field of the Invention
The present invention relates to the field of integrated circuit packaging and, in particular, to wafer level chip scale packaging processes and structures.
2. Description of Related Art
In the prior art, wafer level chip scale packaging techniques typically involved adding various layers to integrated circuit wafers and then patterning the layers using a complex series of masking and photo etching steps. Typically, additive layers were spun-on, sprayed-on as a vapor, or printed on the integrated circuit wafers. As noted above, prior art techniques also typically required the use of photoimagable materials such as Cyclotone™ products or polyimides and the use of extensive photo-definition processes, i.e., masking and photo-etching of the layers.
In the prior art, many of the coatings or layers discussed above, such as photoresist, were not permanent, and did not remain part of the finished product. Rather, many layers were used as temporary masks and were later removed. Consequently, the prior art techniques required multiple steps and significant amounts of discarded/wasted materials. In addition, the process of depositing the prior art layers described above, and then subsequently photo-patterning and photo-etching the layers, was inherently expensive and labor intensive as well as time consuming and complicated.
In addition, the prior art photoimagable materials had to be of specific and limited thickness for the prior art processes to work, and be practical. In the prior art, these thicknesses were typically limited to less than twenty (20) microns. Consequently, the resulting structures typically offered limited flexibility and opportunity for “compliance” between interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
What is needed is a wafer level chip scale packaging method and structure that is not dependent on photolithography and therefore eliminates the need for photoimagable materials, non-permanent layers and the wasteful photo-definition process and makes feasible structures that would be impractical using prior art methods.